1. Field of the Invention
The present invention relates to a plasma display apparatus, and more particularly, to a plasma display apparatus for improving a construction of a driving signal to be adapted to a single scan method and a driving method thereof. Further, the present invention relates to a plasma display apparatus and a driving method thereof, for preventing erroneous discharge and abnormal discharge, enhancing a darkroom contrast, and securing an operation margin.
2. Description of the Background Art
Plasma display apparatus displays an image by exciting and emitting a phosphor using ultraviolet rays generated when an inert mixture gas is discharged. In the plasma display apparatus, thinning and large-sizing are not only easy but also a quality of picture is improved owing to a recent development of technology.
In order to embody the gray level of the image, the plasma display apparatus is time-division driven with one frame divided into several subfields having a different number of times of emission. Each subfield is divided into a reset period for initializing a whole screen, an address period for selecting a scan line and selecting a discharge cell at the selected scan line, and a sustain period for embodying the gray level depending on the number of times of discharge. For example, when the image is displayed at 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields (SF1 to SF8) as in FIG. 1. Each of the eight subfields (SF1 to SF8) is divided into the reset period, the address period, and the sustain period as described above. The reset period and the address period of each subfield are the same at each subfield whereas the sustain period and the number of sustain pulses allocated to the sustain period are increased at a rate of 2n (n=0, 1, 2, 3, 4, 5, 6, 7) at each subfield.
FIG. 2 schematically illustrates an electrode arrangement of a conventional three-electrode alternating current surface discharge type plasma display panel (Hereinafter, referred to as “PDP”).
Referring to FIG. 2, the conventional three-electrode alternating current surface discharge type PDP includes scan electrodes (Y1 to Yn) and a sustain electrode (Z) formed at an upper substrate, and address electrodes (X1 to Xm) formed at a lower substrate to vertically intersect with the scan electrodes (Y1 to Yn) and the sustain electrode (Z).
Discharge cells 1 for displaying any one of red, green, and blue are arranged in matrix at intersections of the scan electrodes (Y1 to Yn), the sustain electrode (Z), and the address electrodes (X1 to Xm).
A dielectric layer and an MgO protective layer not shown are layered on the upper substrate where the scan electrodes (Y1 to Yn) and the sustain electrode (Z) are formed.
A barrier rib for preventing optical and electrical jamming between adjacent discharge cells 1 is formed on the lower substrate where the address electrodes (X1 to Xm) are formed.
The phosphor excited by the ultraviolet rays and emitting visible rays is formed at the lower substrate and a surface of the barrier rib.
The inert mixture gas, such as He+Xe, Ne+Xe, and He+Xe+Ne, is injected into a discharge space between the upper substrate and the lower substrate of the PDP.
FIG. 3 illustrates a driving waveform applied to the conventional PDP of FIG. 2. The driving waveform of FIG. 3 will be described with reference to distributions of wall charges of FIGS. 4A to 4E.
Referring to FIG. 3, each of the subfields (SFn−1 and SFn) includes the reset period (RP) for initializing the discharge cells 1 of the whole screen, the address period (AP) for selecting the discharge cell, the sustain period (SP) for sustaining the discharge of the selected discharge cell 1, and an erasure period (EP) for erasing wall charges within the discharge cell 1.
In the erasure period (EP) of the (n−1)th sub field (SFn−1), an erasure ramp waveform (ERR) is applied to the sustain electrode (Z). During the erasure period (EP), 0V is applied to the scan electrode (Y) and the address electrode (X). The erasure ramp waveform (ERR) is a positive ramp waveform that gradually increases from 0V to a positive sustain voltage (Vs). By the erasure ramp waveform (ERR), erasure discharge occurs between the scan electrode (Y) and the sustain electrode (Z) within on-cells where the sustain discharge occurs. By the erasure discharge, the wall charges within the on-cells are erased. As a result, each of the discharge cells 1 has the distribution of wall charges as shown in FIG. 4A soon after the erasure period (EP).
In a setup period (SU) of the reset period (RP) at which the nth subfield (SFn) initiates, a positive ramp waveform (PR) is applied to the scan electrode (Y), and 0V is applied to the sustain electrode (Z) and the address electrode (X). By the positive ramp waveform (PR) of the setup period (SU), a voltage of the scan electrode (Y) gradually increases from a positive sustain voltage (Vs) to a reset voltage (Vr) higher than the positive sustain voltage. By the positive ramp waveform (PR), a dark discharge not almost generating light is generated between the scan electrode (Y) and the address electrode (X) within the discharge cells of a whole screen, and at the same time, the dark discharge is generated even between the scan electrode (Y) and the sustain electrode (Z). As a result of the dark discharge, soon after the setup period (SU), positive wall charges remain on the address electrode (X) and the sustain electrode (Z), and negative wall charges remain on the scan electrode (Y) as shown in FIG. 4B. While the dark discharge is generated in the setup period (SU), a gap voltage (Vg) between the scan electrode (Y) and the sustain electrode (Z) and a gap voltage between the scan electrode (Y) and the address electrode (X) are initialized to a voltage close to a firing voltage (Vf) capable of generating the discharge.
Consequently to the setup period (SU), a negative ramp waveform (NR) is applied to the scan electrode (Y) in the setdown period (SD) of the reset period (RP). At the same time, the positive sustain voltage (Vs) is applied to the sustain electrode (Z), and 0V is applied to the address electrode (X). By the negative ramp waveform (NR), the voltage of the scan electrode (Y) gradually decreases from the positive sustain voltage (Vs) to a negative erasure voltage (Ve). By the negative ramp waveform (NR), the dark discharge is generated between the scan electrode (Y) and the address electrode (X) within the discharge cell of the whole screen and at the same time, the dark discharge is generated even between the scan electrode (Y) and the sustain electrode (Z). As a result of the dark discharge of the setdown period (SD), the distributions of wall charges within the respective discharge cells 1 are changed to addressable condition as shown in FIG. 4C. At this time, excessive wall charges unnecessary for an address discharge are erased from and a predetermined amount of wall charges remains on the scan electrode (Y) and the address electrode (X) within the respective discharge cells 1. While the negative wall charges are moved from the scan electrode (Y) and accumulated on the sustain electrode (Z), the wall charges on the sustain electrode (Z) are inverted from a positive polarity to a negative polarity. While the dark discharge is generated in the setdown period (SD) of the reset period (RP), a gap voltage between the scan electrode (Y) and the sustain electrode (Z) and a gap voltage between the scan electrode (Y) and the address electrode (X) gets close to the firing voltage (Vf).
In the address period (AP), a negative scan pulse (−SCNP) is sequentially applied to the scan electrode (Y) and at the same time, a positive data pulse (DP) is applied to the address electrode (X) in synchronization with the scan pulse (−SCNP). A voltage of the scan pulse (−SCNP) is a scan pulse (Vsc) decreasing from 0V or the negative scan reference voltage (Vyb) close to 0V to the negative scan voltage (−Vy). A voltage of the data pulse (DP) is the positive data voltage (Va). During the address period (AP), the positive Z bias voltage (Vzb) lower than the positive sustain voltage (Vs) is supplied to the sustain electrode (Z). Soon after the reset period (RP), in a state where the gap voltage is adjusted to be close to the firing voltage (Vf), the gap voltage between the scan electrode (Y) and the address electrode (X) exceeds the firing voltage (Vf) within the on-cells to which the scan voltage (Vsc) and the data voltage (Va) are applied while generating a primary address discharge between the electrodes (X and Y). The primary address discharge between the scan electrode (Y) and the address electrode (X) occurs near an edge distant from a gap between the scan electrode (Y) and the sustain electrode (Z). The primary address discharge generates priming charged particles within the discharge cell, and induces a second discharge between the scan electrode (Y) and the sustain electrode (Z) as shown in FIG. 4D. The distribution of wall charges within the on-cells generating the address discharge is shown as in FIG. 4E.
Meantime, distributions of wall charges within off-cells not generating the address discharge are substantially sustained to be in a state of FIG. 4C.
In the sustain period (SP), the sustain pulses (SUSP) of the positive sustain voltage (Vs) are alternately applied to the scan electrode (Y) and the sustain electrode (Z). If so, in the on-cells selected by the address discharge, the sustain discharge occurs between the scan electrode (Y) and the sustain electrode (Z) at each sustain pulse (SUSP) owing to the distribution of wall charges of FIG. 4E. On the contrary, in the off-cells, the discharge does not occur during the sustain period. This is because, since the distributions of wall charges of the off-cells are substantially sustained to be in the state of FIG. 4C, when the positive sustain voltage (Vs) is initially applied, the gap voltage between the scan electrode (Y) and the sustain electrode (Z) cannot exceed the firing voltage (Vf).
However, the conventional plasma display apparatus has a drawback in that, in a PDP where the subfields are increased in number so as to reduce a factor of deteriorating the quality of picture such as a contour noise, a high-resolution PDP accompanying increase of the number of lines, or a high Xe-content PDP having a great discharge delay, the address period is increased and accordingly, the sustain period being a display period is relatively insufficient. There has ever been proposed a double scan method where the address electrode (X) is two-divided and the divided address electrodes (X) are driven using mutually different address driving integrated circuits, not in a single scan method where all lines are sequentially scanned, in order to reduce the address period. The double scan method has a drawback in that, due to addition of the driving integrated circuit, a circuit cost increases and a noise appears on a divided line. Further, there has ever been proposed a dual scan method where the address electrode is not divided and the scan pulses are partially overlapped, thereby concurrently scanning plural lines. However, the dual scan method has a drawback of causing reduction of a resolution. In the conventional plasma display apparatus, as shown in FIG. 4D, since the address discharge includes a primary discharge between the scan electrode (Y) and the address electrode (X), and a secondary discharge between the scan electrode (Y) and the sustain electrode (Z) using the primary discharge, a time necessary for the discharge is relatively long. Therefore, in the conventional plasma display apparatus, even by a discharge mechanism of the address discharge, the address period gets long.
Further, in the conventional plasma display apparatus, there is a drawback in that, during the erasure period (EP) of the (n−1)th subfield (SFn−1) and the reset period (RP) of the nth subfield (SFn), the discharge is generated at several times to initialize the discharge cells 1 and control the wall charges, thereby reducing the darkroom contrast and reducing a contrast ratio. Table 1 below is an arrangement of a type and the number of times of discharge generated in the erasure period (EP) and the reset period (RP) of the previous subfield (SFn−1) in the conventional plasma display apparatus.
TABLE 1Operation periodRP of SFnCell stateEP of SFn-1SUSDOn-cell turnedOpposite discharge (Y-X)X◯◯on in SFn-1Surface discharge (Y-Z)◯◯◯Off-cell turnedOpposite discharge (Y-X)X◯◯off in SFn-1Surface discharge (Y-Z)X◯◯
As appreciated from the Table 1, in the on-cells turned on in the (n−1)th subfield (SFn−1), during the erasure period (EP) and the reset period (RP), a surface discharge between the scan electrode (Y) and the sustain electrode (Z) is generated at three times, and an opposite discharge between the scan electrode and the address electrode is generated at two times. Further, in the off-cells turned off in the previous subfield (SFn), during the erasure period (EP) and the reset period (RP), the surface discharge between the scan electrode (Y) and the sustain electrode (Z) is generated at two times, and the opposite discharge between the scan electrode (Y) and the address electrode (X) is generated at two times.
The discharges generated at several times in the erasure period and the reset period increase an amount of emission in the erasure period and the reset period where the amount of emission should be minimized if at all possible in consideration of a contrast characteristic, thereby causing reduction of the darkroom contrast value. In particular, the surface discharge between the scan electrode (Y) and the sustain electrode (Z) provides a large amount of emission of light in comparison to the opposite discharge between the scan electrode (Y) and the address electrode (X) and therefore, has a greater bad influence on the darkroom contrast in comparison with the opposite discharge.
Further, in the conventional plasma display apparatus, in the erasure period (EP) of the (n−1)th subfield (SFn−1), the wall charges are not well erased and therefore, the negative wall charges are excessively accumulated on the scan electrode (Y), thereby not generating the dark discharge in the setup period (SU) of the nth subfield (SFn). If the dark discharge is not normally generated in the setup period (SU), the discharge cells are not ideally initialized. In order to stably generate the discharge in the setup period (SU) within the discharge cells where excessive negative wall charges are accumulated on the scan electrode (Y) before the dark discharge of the setup period (SU), the reset voltage (Vr) should be much more increased. Further, if the dark discharge is not generated in the setup period (SU), the discharge cell is not in the optimal address condition soon after the reset period, thereby causing an abnormal discharge or an erroneous discharge. Furthermore, in case where the positive wall charges are excessively accumulated on the scan electrode (Y) soon after the erasure period (EP) of the (n−1)th subfield (SFn−1), in the setup period (SU) of the nth subfield (SFn), when the positive sustain voltage (Vs) being an initiation voltage of the positive ramp waveform (PR) is applied to the scan electrode (Y), the discharge is strongly generated, thereby not uniformly initializing the whole cells. The above drawbacks will be described with reference to FIG. 5.
FIG. 5 illustrates the external application voltage (Vyz) between the scan electrode (Y) and the sustain electrode (Z) and the gap voltage (Vg) within the discharge cell in the setup period (SU). In FIG. 5, the external application voltage indicated by a solid line is an external voltage applied to each of the scan electrode (Y) and the sustain electrode (Z), and is substantially the same as the voltage of the positive ramp waveform (PR) since 0V is applied to the sustain electrode (Z). In FIG. 5, dotted lines {circle around (1)}, {circle around (2)}, and {circle around (3)} denote the gap voltages (Vg) provided for a discharge gas by the wall charges within the discharge cell. The gap voltage (Vg) is varied as in the dotted lines {circle around (1)}, {circle around (2)}, and {circle around (3)} since the wall charges within the discharge cell are varied in amount depending on whether or not the discharge is generated in the previous subfield. A relation of the external application voltage (Vyz) between the scan electrode (Y) and the sustain electrode (Z) and the gap voltage (Vg) provided for the discharge gas within the discharge cell is expressed in Equation 1 below.Vyz=Vg+Vw  [Equation 1]
In FIG. 5, at the gap voltage (Vg) of the dotted line {circle around (1)}, the wall charges are sufficiently erased within the discharge cell, thereby sufficiently reducing the wall charges, and when the gap voltage (Vg) increases in proportional to the external application voltage (Vyz) and reaches the discharge firing voltage (Vf), the dark discharge is generated. By this dark discharge, the gap voltage within the discharge cells is initialized to the discharge firing voltage (Vf).
In FIG. 5, at the gap voltage (Vg) of the dotted line {circle around (2)}, a strong discharge is generated during the erasure period of the (n−1)th subfield (SFn−1), thereby inverting polarities of the wall charges in the wall charge distribution within the discharge cells. At this time, soon after the erasure period (EP), the polarities of the wall charges accumulated on the scan electrode (Y) are inverted into the positive polarities due to the strong discharge. This case is frequently caused by low uniformities of the discharge cells or variation of a slope of the erasure ramp waveform (ERR) depending on temperature variation. In this case, the initial gap voltage (Vg) relatively increases as in the dotted line {circle around (2)} of FIG. 5 and therefore, in the setup period (SU), the positive sustain voltage (Vs) is applied to the scan electrode (Y) and at the same time, the gap voltage (Vg) exceeds the discharge firing voltage (Vf), thereby generating the strong discharge. By this strong discharge, in the setup period (SU) and the setdown period (SD), the discharge cells are not initialized to be in the wall charge distribution of the optimal address condition, that is, in the wall charge distribution of FIG. 4C. Therefore, in the off-cells that should be turned off, the address discharge can be generated. In other words, when the erasure discharge is strongly generated in the erasure period prior to the reset period, the erroneous discharge can be caused.
In FIG. 5, at the gap voltage (Vg) of the dotted line {circle around (3)}, during the erasure period (EP) of the (n−1)th subfield (SFn−1), the erasure discharge is not generated or is very weakly generated, thereby maintaining the wall charge distribution within the discharge cells, as it is, formed as a result of the sustain discharge generated just before the erasure discharge. In a detailed description, as in FIG. 3, the last sustain discharge is generated when the sustain pulse (SUSP) is applied to the scan electrode (Y). As a result of the last sustain discharge, the negative wall charges remain on the scan electrode (Y), and the positive wall charges remain on the sustain electrode (Z). However, such wall charges should be erased through the erasure discharge in order to perform a normal initialization in a next subfield. But, when the erasure discharge is not generated or is very weakly generated after the last sustain discharge, the polarity is kept as it is. A reason why the erasure discharge is not generated or is very weakly generated is that in the PDP, the discharge cells are low in uniformity or the erasure ramp waveform (ERR) is varied in slope depending on the temperature variation. In this case, the initial gap voltage (Vg) is much low to have the negative polarity as in the dotted line {circle around (3)} of FIG. 5 and therefore, even though the positive ramp waveform (PR) increases up to the reset voltage (Vr) in the setup period, the gap voltage (Vg) within the discharge cells does not reach the discharge firing voltage (Vf). Therefore, the dark discharge is not generated in the setup period (SU) and the setdown period (SD). As a result, in case where the erasure discharge is not generated or is very weakly generated in the erasure period prior to the reset period, the initialization is not normally performed, thereby causing the erroneous discharge or the abnormal discharge.
In the dotted line {circle around (2)} of FIG. 5, the relation of the gap voltage (Vg) and the discharge firing voltage (Vf) is expressed as in Equation 2, and in the dotted line {circle around (3)} of FIG. 5, the relation of the gap voltage (Vg) and the discharge firing voltage (Vf) is expressed as in Equation 3:Vgini+Vs>Vf  [Equation 2]Vgini+Vr<Vf  [Equation 3]
where,
Vgini: initial gap voltage just before the setup period (SU) is initiated as appreciated from FIG. 5.
A gap voltage condition (or wall charge condition) for performing the normal initialization in the erasure period (EP) and the reset period (RP) considering the above drawbacks is expressed in the following Equation 4 satisfying all of the Equations 2 and 3:Vf−Vr<Vgini<Vf−Vs  [Equation 4]
Resultantly, if the initial gap voltage (Vgini) does not satisfy the condition of the Equation 4 before the setup period (SU), the conventional plasma display apparatus can cause the erroneous discharge, the misdischarge, or the abnormal discharge, and decreases the operation margin. In other words, in the conventional plasma display apparatus, in order to secure the operation reliability and the operation margin, an erasure operation in the erasure period (EP) should be normally performed but, as aforementioned, can be abnormally performed depending on the uniformity of the discharge cell or the use temperature of the PDP.
Further, in the conventional plasma display apparatus, the wall charges accumulated on the scan electrode (Y) and the sustain electrode (Z) before the reset period are not sufficient and therefore, the setup discharge occurs near the reset voltage (Vr) higher (100 V or more) than the sustain voltage (Vs). Due to this, the conventional plasma display apparatus has a drawback in that an external applied voltage is increased for the setup discharge and as a result, high voltage devices should be included in a voltage source generating a high voltage and a scan drive circuit, thereby increasing a cost of the scan drive circuit.